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Faculty Profile

Mr. Anjan Kumar
Asstt. Professor
Institute of Engineering and Technology
Department of Electronics & Communications

Contact Details:

Email: anjan.kumar@gla.ac.in
Contact Number: 8449431935

Area of Research Interest

  • Low Power/Low Voltage Electronics
  • Characterization and Design of Low Power Logic and Memory
  • Leakage Power Reduction and Ground Bounce Noise Reduction Techniques
  • Power-Gated Arithmetic Circuits for Energy-Precision.
  • Process Variation Aware Power Gating Techniques
  • Distributed Data-Retention Power Gating Techniques for Embedded SRAM.
  • Microprocessor and Micro-controller  based system

 Educational Qualifications

  • M.Tech(VLSI Design ),Indian Institute of Information Technology & Maagement,Gwalior.  (Year-2012)
  • B.Tech.(Electronics and Communication),Cochin University of science and technology Kochi kerala.(Year-2006)

 Professional Experience

  • Working as Assistant Professor at G.L.A.University, Mathura,(U.P) since 19thFebruary 2007.

Honors/Achievements/Recognition

  • Awarded best Faculty Award-2017 by GLA University,Mathura

 Research Publications

Journal

  • Anjan Kumar, Shashikant Sharma,  Manisha Pattanaik, and Balwinder Raj, " Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders,"International Journal of Information and Electronics Engineering vol. 3, no. 6, pp. 567-572, 2013. 
  • Manisha Pattanaik, Balwinder Raj,and Shashikant Sharma and Anjan Kumar  ,” Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders ”,  International Conference on Electronics, Nanomaterials and Components, Advanced Materials Research Journal, Vol. 548, pp. 885-889, China 2012. 
  • Kumar A., Sharma G. K., Kumar A., Agrawal T., Srivastava V, “Design of energy efficient random access memory circuit using stub series terminated logic i/o standard on 28nm FPGA,” Asian Journal of Science and Technology, vol. 6(8), August, 2015. (IET and EBSCO indexed)

 INTERNATIONAL CONFERENCES

 

  • Kumar Anjan., Sharma G.K., Agrawal T., Agrawal D., “Designing of Random AccessMemory Using Different IO Standard Technology,” in Proceedings of 7thInternational Conference on Computing, Communication and Networking Technologies), ICCCNT '16, July 06-08, 2016, Dallas, TX, USA 2016 ACM ISBN:978-1-4503-4179-0/16/07DOI: http://dx.doi.org/10.1145/2967878.2967913.
  • Solanki S., Kumar A. and Dubey R., “Stacked Transistor based multimode power efficient MTCMOS full adder design in 90nm CMOS technology,” in proceedings of 6th IEEE International Conference on Communication and Signal Processing (ICCSP-16), Melmaruvathur, Tamilnadu.pp:663-667
  • Kumar A., Agrawal T., Srivastava V., “Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA,” in proceedings of International Conference on Computational Intelligence and Communication Networks (CICN - 2015), pp. 1334 - 1337, 2015.
  •  Solanki S., Kumar A. and Dubey R., “Multimode MTCMOS technique for reactivation noise Minimization in 8T FULL adder circuit,” in proceedings of6thIEEEInternational Conference on Communication Systems and Network Technologies (CSNT-2016), Chitkara University Chandigarh.
  • Solanki S., Kumar A. and Dubey R., “Stacked Transistor based multimode power efficient MTCMOS full adder design in 90nm CMOS technology,” in proceedings of 6th IEEE International Conference on Communication and Signal Processing (ICCSP-16), Melmaruvathur, Tamilnadu.pp:663-667
  • Kumar A., Agrawal T., Srivastava V., “Designing of Power Efficient ROM UsingLVTTL and Mobile-DDR IO Standard on 28nm FPGA,” in proceedings of International Conference on Computational Intelligence and Communication Networks (CICN - 2015), pp. 1334 - 1337, 2015.
  • Agrawal N., Agarwal M., Singh S., Kumar A., Pandey B.P., “Different I/O standard based Wi-Fi enable 32-bit ALU design on 90nm FPGA,” in proceedings of IEEEinternational conference on Communication, Control and Intelligent Systems (CCIS - 2015), pp. 382 - 389, 2015.
  • Dubey R., Kumar A., Pattanaik M., “Design of low noise low power two stage CMOS operational amplifier using Equivalent Transistor Replacement Technique for health monitoring applications,” in proceedings of 5thInternational Conference onComputing, Communication and Networking Technologies (ICCCNT), pp. 1-6, 2014,11-13 July 2014,Hefei, China.
  • Agarwal M., Singh S., Agrawal N., Kumar A., Pandey B. P., “Frequency scaling based thermally tolerable Wi-Fi Enable 32-bit ALU design on 90nm FPGA,” in proceedings of Communication, Control and Intelligent Systems (CCIS - 2015), pp. 376-381, 2015, GLA University, Mathura, India.
  • Dubey  R.,  Kumar  A.,  Pattanaik  M.,  “Design  of  low  noise  low  power biopotentialtunable amplifier using voltage controlled pseudo-resistor for biosignal acquisition applications,” in proceedings of 5thInternational Conferenceon Computing, Communication and Networking Technologies (ICCCNT), 2014, pp.1-5, 11-13 July 2014,Hefei, China.
  • Kumar A., Sharma S. and Pattanaik, M., “Reactivation Noise Aware Data PreservingMulti-Mode MTCMOS Shift Register,” in proceedings of International Conferenceon Computing, Communication and Networking Technologies (ICCCNT), pp. 1-5, 26-28 July 2012.
  • Kumar A., Sharma S. and Pattanaik M., “A Novel Data Preserving Multi-Mode MTCMOS Shift Register for Ground Bounce Noise Minimization,” in proceedings of 4thIEEE International Conference on Electronics Computer Technology, pp. 654-658, 2012, Kanyakumari, India.
  • Anjan Kumar, Shelesh Krishna Saraswat and Tarun Agrawal “Design of 4- bit LFSRon FPGA” 8th International Conference on Computing, Communication and Networking Technologies (8th ICCCNT 2017) IIT Delhi. 
  • Shashikant Sharma, Anjan Kumar, Manisha Pattanaik and Balwinder Raj “Leakage Current and Ground Bounce Noise Aware Nano MTCMOS Adder Circuits“ Proceedings of National Symposium on Recent Advances in NanoScience Engineering and Technology, ABV-IIITM Gwalior, India
  • Preeti Agrawal, Anjan Kumar“Diode based Multi Mode MTCMOS 8T adder for Wake up Noise Minimization in 90nm CMOS Technologies” 8th International Conference on Computing, Communication and Networking Technologies (8th ICCCNT 2017) IIT Delhi.
  • Anjan Kumar, Devendra Chack and Manisha Pattanaik “Low Leakage Sequential MTCMOS Shift Register For Mitigation of Ground Fluctuations Noise During Complete Reactivation Process” In proceedings of  3rd  International Conference on Internet of Things (IoT) and connected technologies, MNIT Jaipur.
  • Harekrishna Kumar,Anjan Kumar and Vinay Deolia “Core i7 Specific Energy Efficient RAM Design for IoT Application” In proceedings of  3rd  International Conference on Internet of Things (IoT) and connected technologies, MNIT Jaipur.
  • Harekrishna kumar,Anjan kumar,Vinaykumar Deolia Enabling Concurrent Clock and Power Gating in 32 Bit ROM “ 9th international conference on computing, communication and networking technologies (icccnt)2018”IISc Bengaluru
  • Tarun Agrawal, Anjan Kumar, Priyanka ., Pooja Aggarwal and Syed Saad Tirmizi “LVCMOS Based 4-Bit Register 9th international conference on computing, communication and networking technologies (icccnt)2018”IISc Bengaluru.
  • Tarun Agrawal, Anjan Kumar and Juhi Sharma “Environment Friendly Frequency Scaling based counter design” 9th international conference on computing, communication and networking technologies (icccnt)2018”IISc Bengaluru
  • Shelesh Krishna Saraswat, Anjan Kumar and Tarun Agrawal “ Synthesis and Simulation of efficient CAM” 8th International Conference on Computing, Communication and Networking Technologies (8th ICCCNT 2017) IIT Delhi.

 

 National Conference

  • Shashikant Sharma, Anjan Kumar, Manisha Pattanaik and Balwinder Raj “Leakage Current and Ground Bounce Noise Aware Nano MTCMOS Adder Circuits“ Proceedings of National Symposium on Recent Advances in Nano Science Engineering and Technology, ABV-IIITM Gwalior, India

Industrial Projects Guided

“Design and Simulation of Electronic Instruments for Mobile Solar Weather system” for BKC WeatherSys Pvt. Ltd.Noida

No of Post-graduate thesis guided -05

No of B.tech project guided-28