- 9.5 years Teaching experience in the field of Electronics and Communication.
PhD (pursuing): GLA University, Mathura, U.P., India. (Enrolled in year 2016)
M.Tech. (2013): Uttar Pradesh Technical University, Lucknow, U.P.
- “Explicit Timing Analysis of Discontinuous RC Global VLSI Interconnect Lines under Ramp Input”, Journal of Electron Devices, Vol. 15, 2012, pp. 1249-1253.
- “Closed Form Expressions for Extending Step Delay to Ramp Inputs for On-Chip VLSI RC Interconnect” National Conference on Emerging trends in Electrical Instrumentation and Communication Engineering, Agra, April 6-7, 2012
- “Evaluation of Slew Metric Ramp Inputs for On-Chip VLSI RC Interconnect”, National Conference on Emerging trends in Electrical Instrumentation and Communication Engineering, Agra, April 6-7, 2012
- “Elmore's approximations based Explicit Delay and Rise Time Model for Distributed RLC On-Chip VLSI Global Interconnect”, IEEE Symposium on Humanities, Science and Engineering Research, Singapore, 24-27 June 2012, Page(s): 1135 - 1139
- “Moment based Delay Modelling for On-Chip RC Global VLSI Interconnect for Unit Ramp Input” International Joint Conference on Computer Science and Software Engineering (JCSSE) ,Bangkok, Thailand, May 30 2012-June 1 2012, Page(s): 164 – 167
Postgraduate Thesis Supervised
Completed/ Awarded : 3
Working : 1
Conferences/ Seminars/Workshops Attended